Tensor tucker decomposition accelerated on FPGA for convolution layer compress

The tensor data format has become popular due to the large number of CNN parameters and the increased storage requirements. While it has the potential to address various scientific and engineering challenges, applying it to limitedre-source devices can be difficult. Therefore, the primary focus of this research is to utilize hardware to enhance the speed of neural network prediction while maintaining the accuracy of the original network. We have implemented relevant modules, such as the tensor multiplied matrix (TMM) module and the matrix singular value decomposition (SVD) method, using ZYNQ FPGA. We constructed the LeNet-5 model, extracted its convolution layer parameters, decomposed them on the hardware side, and compared the outcomes. By verifying the design on an FPGA, the final results show that a 10.5 times acceleration ratio is achieved compared to the CPU platform.