Approximate Binary Stacking Counters For Error Tolerant Computing Multipliers

To increase the power and efficiency of VLSI circuits, a new, creative multiplying methodology is required. Multiplication is a crucial arithmetic operation for many of these applications. As a result, the newly proposed error-tolerant computing multiplier is a crucial component in the design of approximate multipliers that are both power and gate efficient. We have created approximative multipliers for several operand lengths using this suggested method and a 45-nm library. Depending on their probability, the approximation for the accumulation of changing partial products varies. In compared to approximate multipliers that were previously given, the proposed circuit produces better results. When column-wise generate elements are added to the modified partial product matrix using an OR gate, the output is usually accurate. The amount of energy used, and its silicon area have been considerably reduced in the suggested multiplier when compared to traditional multipliers by 41.92% and 18.47%, respectively. One of the platforms that these suggested multipliers are suitable for is the image processing application.