Design of a 4–2 Compressor-based Approach for Efficient Approximate Multiplier Design

One Crucial technical edge for the futureis energy-efficient computing. A computing paradigm known as approximate or inexact computing allows for the tradeoff between processing time energy efficiency and output precision. In this project, an approximatecompressor with reduced size, delay, and power is presented, along with an approximate design and analysis. The recommended compressors are used to implement the
$8 \ \mathrm{x} \ 8$
and
$16 \ \mathrm{x} \ 16$
Wallace tree multipliers. When these multipliers are compared to the most advanced approximation multipliers, they exhibit great accuracy. The 45nm CMOS technology is used to execute the suggestedstrategy, and its efficacy is thoroughly assessed. across various metrics including area, power, delay. For the
$8 \ \mathrm{x} \ 8$
Wallace tree multiplier, the proposed approximate 4–2 compressor exhibits a significant decrease of 18.10% in power, 26.4% in area, and 68.84% in delay. It also exhibits a significant reduction of 22.7% in power. For the 8
$\mathrm{x} \ 8$
Wallace tree multiplier, the proposed approximate 4–2 compressor exhibits a significant decrease of 18.10% in power, 26.4% in area, and 68.84
^%
in delay. It also exhibits a significant reduction of 22.7% in power, a 40.34% decrease in area, and a40.34
^%
decrease in delay for the
$16 \mathrm{x}16$
Wallace tree multiplier when compared to an accurate 4–2 compressor. The analysis extends to explore the potential applications of the suggested architecture in error-tolerant applications like image Sobel edge detection.