Design and Simulation of AXI4 Stream Interconnect Using Verilog

System-on-a-chip (SoC) designs depend on the Advanced eXtensible Interface (AXI) 4 protocol and essentially AXI4 stream protocol, which enables fast data transfers between multiple master and slaves through interconnect architecture. The development of an AXI 4 Stream protocol interconnect setup with one master and two slave modules, simulated under Verilog HDL, is shown in this work using a unique technique. We optimize the connection architecture for reliable data transfer using round robin algorithm. The findings show that the suggested configuration guarantees reliable data processing and resilience in a multi-slave context in addition to complying with the AXI4 stream protocol criteria.