Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths

This paper delves into the application of Field Programmable Gate Arrays (FPGAs) in both the design and enhancement of adders, pivotal components within digital systems. Five widely used adder architectures - Ripple Carry Adder, Carry Skip Adder, Carry Select Adder, Carry Look Ahead Adder, and Kogge Stone Adder - undergo rigorous evaluation. Leveraging the robust capabilities of Xilinx Vivado software, a comprehensive assessment of adder performance metrics, including delay, power consumption, temperature, and area utilization, is conducted across varying bit lengths (4bit to 32bit). Furthermore, practical implementation using the Basys 3 Xilinx Artix-7TM FPGA Board is executed. This meticulous analysis facilitates the identification of the most efficient adder architecture tailored to diverse bit lengths, thereby significantly enhancing the functionality and performance of digital systems across various applications.