Design of Accurate, Power and Area Efficient 16X16 Multiplier using Approximation Techniques

Effective multiplication is necessary in high-power computer applications like signal and image processing. Even though approximate arithmetic compromises output precision, it presents an achievable path towards designing energy-efficient digital systems with minimal environmental impact. The paper outlines the design of approximate multipliers, utilizing both conventional and approximate Half Adders & Full Adders by strategically placing for adding partial products at the Most Significant Bit (MSB) positions and OR gates are utilized to add the partial products at the Lower Significant Bit (LSB) positions. In addition, this research paper shows the 16x16 multipliers of unsigned and signed by incorporating clock gating for enhanced power reduction. The Verilog HDL implementation the proposed multiplier includes simulations using Artix-7 AC701 FPGA on Xilinx VIVADO design tool. The results found that an enhance accuracy while potentially reducing power usage by 11.8% and 15.8%.