Implementation of NMOS-based LDO Using Recycling Folded-Cascode in 16 nm FinFET

This paper presents the design and implementation of a robust conventional NMOS-based Low Dropout Regulator (LDO) in 16nm FinFET. The LDO features a recycling folded-cascode as error amplifier with a supply voltage ranging from 1.028V to 1.32V and a programmable output voltage from 0.4V to 0.9V. The primary objective of this work is to achieve the optimal balance between various specifications including DC gain, Power Supply Rejection Ratio (PSRR), silicon area, and line/load regulation response. The robustness of the LDO design was thoroughly validated at the schematic level under 516 Process, Voltage, and Temperature (PVT) corners, as well as through Monte Carlo (MC) Simulations. The designed LDO, occupying an estimated area of 2696.8 μm
²
, demonstrates a mean DC gain of 74.87dB, PSRR at 10kHz of −76.28dB, and PSRR at 1MHz of −36.29db. Additionally, the LDO consistently maintains a phase margin exceeding 65°. The proposed LDO is compared with the current state of the art.