Implementation of Full Adder Cells for Ultra Low Power Energy Efficient Computing Applications

Energy Efficiency is of critical significance when designing integrated circuits. In the world of advanced integrated circuits that operate in near-threshold voltage is gaining much awareness because of its potential for high-performance and energy-efficient designs. Today's VLSI design places a great deal of importance on static or leaky power usage as technology advances into the nanoscale realm. In this brief, a one-bit full adder cell with reduced transistor count is suggested for lower power application by employing CMOS, Pass Transistor Logic and Transmission Gate schemes with XOR, XNOR and multiplexer logics at different supply voltages for achieving full swing sum and carry output. Post-layout simulation results reveal that, the proposed one-bit full adder design has achieved remarkable improvements compared to other published designs, boasting over 23 % energy savings and over 32% reductions in Energy Delay Product by employing just 10 transistors. The outcomes demonstrate how efficient the full adder cells can serve as an arithmetic circuit for conventional signal processing computing applications in integrated circuits.