A Two-Speed,Radix-4, Parallel-Parallel Multiplier

Digital multiplication is an important task in various computer applications, and increasing its performance is essential to enhance performance and power consumption. This article presents a low-power modified booth multiplier(MBM) design scheme reducing energy consumption while maintaining efficiency. A modified booth algorithm is used to reduce partial production, and several low-power methods are included in the multiplier architecture. The proposed design incorporates optimized booth encoding, low-power arithmetic blocks and pipeline platforms to increase energy efficiency. Clock-gating is creatively used to disable passive components and selectively shuts off unused portions of the power-gating multiplier. Also, parallelism is required to increase speed, and supply voltage scaling is judicially applied to balance power reduction with reliable operation. Simulation results and comparisons with conventional multiplier architectures demonstrate the effectiveness of the low-power scheme. The results reveal a significant reduction in dynamic and static energy consumption, establishing the proposed modified booth theory as a viable alternative low-enrgy battery-powered device. This research is in line with the growing demand for energy-efficient design for modern computing systems that helps to maintain efficiency related to statistical units.