Implement a PnR Flow to Boost the Pin Density in Block Level Chip Design

During the physical design process., it is usual to come across pin density in the placement stage. As cell geometry becomes smaller and smaller pin density plays an important role in timing management and congestion in a physical design process., a higher pin density results in congestion issues., while a lower pin density affects the timing of the integrated circuit. In this research, we present an analysis of the physical design process for a 40nm technology to enhance pin density in less congested regions and improve high-density regions using cell padding and uniform density techniques with the help of the ICC2 tool.