Optimized Parallel Architecture for a Constant-Time Synchronous Binary Counter with Minimal Clock Period

An ideal parallel design for a clock-period-minimal constant-time synchronous binary counter is presented in this paper. The architecture makes use of two types of 8-bit synchronous binary counters: one that uses a ripple carry chain and the other that uses backward carry propagation. In addition, it presents an altered 64-bit prescaled counter that generates prescaled enable signals by means of ring counters. Our proposed design shows considerable benefits over current approaches. Compared to the conventional technique, which has 131 area registers, 68 LUTs, and 66 IOBs, the suggested method uses 99 area registers, 65 LUTs, and 66 IOBs, reducing the area footprint in terms of hardware resources. Furthermore, the suggested architecture reduces latency; the current method's latency is 1.172 ns, but the new architecture's latency is 0.978 ns. Additionally, the suggested approach shows improved power efficiency, using only 0.00107 W as opposed to 0.0162 W for the current method. These findings demonstrate how well the suggested architecture performs in terms of improving performance metrics, which makes it a viable option for applications that call for synchronous binary counters that operate constantly with short clock periods.