An Efficient Approach to Design Ternary Logic Circuits with GNRFETs

This project introduces a novel approach for designing ternary logic circuits using Graphene Nanoribbon Field-Effect Transistors (GNRFETs) and HSPICE software. Emphasizing three states (0, 1, and an intermediate state), ternary logic promises enhanced information processing over binary systems. The study leverages GNRFETs' unique properties, including high carrier mobility, in HSPICE simulations. A systematic approach within HSPICE facilitates custom GNRFET modeling, circuit optimization, and validation of ternary logic gates. Key outcomes emphasize improved computational efficiency, laying the groundwork for future computing advancements. Additionally, the study explores the impact of environmental factors and scaling effects on GNRFET-based ternary circuits, providing insights into their robustness and scalability. Furthermore, the project investigates novel techniques for error tolerance and noise resilience in ternary logic circuits, addressing critical challenges for practical deployment. The comprehensive exploration of GNRFET-based ternary logic signifies a leap in computational capabilities. It sets the stage for innovative applications in emerging technologies, such as neuromorphic computing and advanced data processing paradigms.