Design of a 300mV-Supply Schmitt-Trigger-Based DIGOTA for GBW and DC Gain Enhancement in 16nm FinFET

An ultra-low voltage and power Schmitt-Trigger-Based Digital Operational Transconductance Amplifier (ST-DIGOTA) is proposed here for the first time using 16 nm CMOS FinFET technology. In this design, the inverter gates, whose digital outputs are used to govern the circuit evolution throughout each circuit states, are replaced by Schmitt-Trigger inverters making their own trip points variable. It allows the DIGOTA to stay more time in the states that trigger the output stage increasing then the circuit bandwidth. Similar to others digital-like OTA implementations, the proposed one is designed without the need of any biasing circuit and only used digital standard cells aiming a quick design cycle and porting. For comparison purpose, two DIGOTAs are designed at the same FinFET technology: with (ST-DIGOTA) and without (DIGOTA) Schmitt-Trigger inverters. Even though the ST-DIGOTA floorplan silicon area is 39% larger than DIGOTA, operating at the same supply voltage of only 300 mV, the ST-DIGOTA achieves 70% more Gain-bandwidth product (GBW) and 25dB more DC gain consuming only 451 nW more. Both OTAs are able to drive a capacitive load of 500pF having similar an average slew rate of 2.9 mV/μs for both the ST-DIGOTA and DIGOTA. In light of these results, an area-normalized large signal figure of merit (FOM
LA
) of 36k and 352.6k [(V/μs)·pF/(μW·mm
²
)] are accomplished along with an area-normalized small signal figure of merit (FOM
SA
) of 0.34M and 1.8M [MHz·pF/(μW·mm
²
)] for ST-DIGOTA and DIGOTA, respectively.