Investigation and Subcircuit Modeling of Self-Heating in PDSOI NFETs at Cryogenic Temperatures Using Pulsed I – V Technique for Co-Integrated Quantum Technologies

This article presents an investigation of the thermal effects in 45-nm PDSOI n-channel MOSFETs using a modified pulsed I–V technique at cryogenic temperatures. Isothermal characteristics are successfully extracted from experimentally measured time evolution profiles of the drain current for chuck temperatures ranging from 300 to 10 K. Significant self-heating is observed for the devices at cryogenic temperatures, which degrades their performance and poses a challenge in their application as cryo-electronics for quantum computing and other cryo-applications. Temperature and width dependence of effective thermal resistance is explored, taking into account the layouts and thermal conductivities of different layers. Devices with lower total width experience less self-heating due to weaker thermal coupling. To accurately predict the device behavior, including the thermal effects at cryogenic temperatures, a subcircuit model is proposed to augment the existing industry standard process design kit (PDK) models. The robustness of the proposed model is established for DC as well as isothermal operating conditions over a wide temperature range and for different device geometries.