An Implementation of O-RAN-Based Dynamic Acceleration for Reducing Power Consumption

Sixth-generation (6G) mobile communication systems have been studied to deal with the exponential increase in mobile traffic. Improving the processing load and power consumption will be a challenge for the 6G Radio Access Network (RAN). Simultaneously, RAN virtualization, where the RAN functions are implemented in commodity servers as software, has been developed and commercialized from the viewpoint of reducing cost, scalability, and simplifying operations. Central Processing Units (CPUs) generally execute the virtualized RAN functions. In contrast, hardware offload schemes have been considered, where the implemented GPUs (Graphics Processing Units) and FPGAs (Field Programmable Gate Arrays) run a part of the functions instead of CPUs according to the characteristics of each hardware. For instance, GPU can perform parallel processing faster and more efficiently than CPU, while FPGA can perform routine operations excellently. In addition to these proper selections of execution hardware for each RAN function, we propose an architecture that switches with or without hardware offloading depending on the traffic loads to decrease power consumption. Through experimental evaluation, we measured the energy efficiency of the offloading for each RAN function and overall 5G RAN. Finally, we discuss the threshold of dynamic offloading and estimate the power consumption of a 5G base station from statistical data.