Exploring RISC-V Based DNN Accelerators

As the Internet of Things (IoT) continues to expand, extreme edge devices need to perform diverse operations tailored to various application scenarios. These devices are characterized by limitations on on-chip resources and energy supply. Given the importance of information security and network bandwidth conservation, many researchers have recently turned to deploying Deep Neural Network (DNN) models on resource-constrained devices. This approach enables local data processing, effectively reducing costs and mitigating accuracy trade-offs compared to transmitting large volumes of data to servers. The adoption of DNN accelerators based on the RISe-V Instruction Set Architecture (ISA) in resource-constrained devices has seen a notable increase in recent years. Thanks to their open-source nature, flexibility, and efficiency, these accelerators are driving advancements in performance and energy efficiency for extreme edge devices. This article aims to review recent D NN accelerator designs based on the RISe-V architecture, focusing on open-source designs that have garnered significant interest among researchers and businesses.