A Binary Level Verification Framework for Real-Time Performance of PLC Program in Backhaul/Fronthaul Networks

PLC control programs are vulnerable to real-time threats, where attackers can disrupt the backhaul/front-end network of industrial production by creating numerous loops or I/O operations, leading to severe consequences. Therefore, formal verification of PLC control logic at the binary level is essential. In this study, we introduce a framework designed for formal verification of PLC control logic at the binary level. Our verification framework is based on simulation execution, which extracts the core control logic from PLC binary code. Initially, we develop an efficient framework for automating the parsing of PLC programs at the binary level and constructing their control flow graphs (CFGs). Next, we devise an algorithm to transform the reversed PLC assembly program into an smv model, a widely accepted formal verification tool. Subsequently, we generate real-time requirements relevant to industrial production and perform formal verification on the constructed models. To assess the real-time performance of our framework in safeguarding PLC systems, we implement a prototype and evaluated it across various representative ICS scenarios. The evaluation results demonstrate the capability of our proposed approach to effectively detect synchronization threats in PLC logic control programs.