A Recessed Source Contact Technology to Reduce the Specific On-Resistance of Power MOSFET on 4H-SiC

Reducing the on-resistance of SiC MOSFETs is crucial for lowering power losses and is a key aspect of MOSFET design. This letter proposes a recessed source contact (RSC) process, which utilizes the side contacts of the recessed contact structure to increase the effective contact area after narrowing the contact window width. This technology can reduce cell pitch as well as specific on-resistance without sacrificing other resistance components. In our demonstration of 1.7 kV VDMOSFETs, reducing the cell pitch from $6.2~\mu $ m to $5.0~\mu $ m by shrinking the contact width with the assistance of the RSC structure decreases the specific on-resistance by 12.6%. Conversely, without employing the RSC structure, the specific on-resistance increases by 5%. Furthermore, the RSC process allows for continuous P-well contact. Since the P⁺ contact is embedded under the N⁺ source, the depth and width of the P⁺ layer are not constrained by the N⁺ source layer.