Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration

With the exponential growth of digital information, the demand for efficient and secure data encryption has become ever more critical. The Advanced Encryption Standard (AES) stands as a robust and widely adopted cryptographic algorithm, safeguarding data across diverse applications. However, implementing high-throughput AES-256 efficiently on hardware platforms can be challenging due to its computational complexity and the intricate hardware routing requirements for high-performance implementations. This paper proposes a hardware architecture for a high throughput, fully pipelined AES-256 implementation on FPGAs. The core of this design lies in a significantly optimized S-Box architecture, achieving a substantial reduction in area consumption compared to traditional implementations. This approach makes the design more resource-efficient for resource-constrained platforms. Furthermore, advanced extensible interface (AXI) facilitate seamless integration with external processing systems and data streams, ensuring high throughput and efficient data movement.