Design and Implementation of VHF Radar Signal Processor

In this paper, a signal processing algorithm for VHF radar is designed and implemented. The aim is to realize the radar signal processing on a field programmable gate array (FPGA) platform processor and compare the simulated results with the real outputs and also minimize required FPGA resources to simplify implemented design. The digital signal processing stages: matched filter(MF), moving target indicator(MTI), integration, constant false alarm rate(C-FAR), and binary integrator(BI) have been simulated on Matlab and compared with implemented on the FPGA. ARTIX-7 FPGA (xc7a200tfbg484-2 device) was used to process revived data using the Vivado 2018.2 design tool.