A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces

This article presents a low-power and jitter-filtering-capable clock distribution scheme using a digital phase-locked loop-based (DPLL-based) quadrature clock generator (QCG) for high-speed dynamic random access memory (DRAM) interfaces. The conventional clock distribution distributes four quadrature clock signals at a high frequency of $f_{\mathrm {CLK}}$ to many DQs over long-distance channels, which consumes significant power. On the contrary, the proposed low-power scheme distributes only a single-phase clock at a much lower frequency, i.e., 1/ $8f_{\mathrm {CLK}}$ , so it can reduce the clock distribution power consumption dramatically to 1/32. Then, the proposed QCG generates the precise quadrature clocks with a 25% duty cycle (DC) at $f_{Q\mathrm {CLK}}$ right before DQs. Since the QCG was designed based on a phase-locked loop (PLL) operating at 1/ $8f_{\mathrm {CLK}}$ , it can filter the input clock jitter while consuming less than 1-mW power. Since the proposed QCG uses a frequency-independent method to correct the quadrature error, it can extensively increase the operating range of $f_{Q\mathrm {CLK}}$ . This work also presents the synchronous mode-switching divider (SMS-DIV), enabling an immediate transition between IDLE and ACTIVE modes. The proposed QCG was fabricated in 40-nm CMOS and consumed $900~\mu $ W for generating 2-GHz quadrature output signals. This work achieved a very low quadrature error of less than 0.5° consistently over the frequency range of 1–4 GHz.