A Digitally Controlled CMOS Vector-sum Phase Shifter with Low RMS Phase Error for Ka-band Phased-arrays

In this paper, a digitally controlled vector-sum phase shifter (VMPS) with 5.625-degree step in a 55 nm bulk CMOS process is presented. Specially, the quadrature signal generator utilizes a compact-sized RLC quadrature all-pass filter (QAF) with low insertion loss to generate the desired wideband 0/90-degree quadrature (I/Q) signals. The analog adder, implemented using two Gilbert cells, controls the amplitude and polarity of the I/Q signals by manipulating the logic switches encoding, thereby synthesizing the required phase. Two transformer input/output baluns are employed for achieving good single-to-differential-ended signal conversion and impedance matching. With a 6-bit resolution, the proposed VMPS exhibits excellent overall performance operating in the Ka-band. The measured results, in which the root mean square (RMS) phase error is less than 2.4°, the RMS amplitude error is better than 0.26 dB, cover a 360° phase range over the operating frequencies from 26 to 32 GHz. The measured peak average gain is −7.5 dB at 29 GHz. The VMPS draws a current of 3.2 mA from a 1.5 V supply voltage; the chip occupies a small silicon area of 0.73 mm
²
including all testing pads with a core size of only 0.45 mm
²
. The proposed VMPS has the potential to be used as the individual block or building block in Ka-band phased-array applications.