CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation

Parallelism capability of GPUs makes accelerated RTL simulation possible by utilizing structure-level and data-level parallelism of designs. However, due to the existence of feedback loops in circuits, how to achieve data-level parallelism in a single testbench is still a great challenge. In this paper, we propose a novel CPGPU-accelerated RTL simulation framework with loop unrolling techniques to utilize data-level parallelism for RTL simulation acceleration. In the framework, designs under simulation are first processed by loop unrolling. Then the processed designs are partitioned and the simulation task of each partition is assigned to be simulated on CPU or GPU according to its characteristics. The design partitioning method makes full use of the parallel capabilities of RTL simulation using GPU. The promising experimental results show that the proposed CPGPU-accelerated RTL simulation achieves up to 32.2 ×speed-up than ESSENT and 4.8× speed-up than traditional GPU-based acceleration methods.