A Topology-flattening-based Automated Incremental Synthesis Method

As chip development enters the “post-Moore's Law era,” the core driving force behind chip design is shifting from pursuing enhancements in performance, power, and area (PPA) to constructing autonomous chips for emerging applications. However, due to the gap between domain-specific systems and traditional chip design, the transition from functional requirements to chip designs has become increasingly complex. Logic synthesis, as a tedious and time-consuming step at the front end of the process, is one of the major bottlenecks in accelerating the iterative development of chip designs. This paper proposes an automated incremental logic synthesis technique based on topological-flattening. This paper performs incremental synthesis based on files, such that when modifications occur, only the files containing the modified parts undergo re-synthesis. Building upon this technique, we have developed an automated synthesis system that can flexibly integrate existing open-source synthesis tools to achieve automated incremental synthesis. Experimental testing conducted on Yosys demonstrates that our proposed method enhances the iteration efficiency of chip design front-end, providing an effective solution for rapidly generating hardware code that meet design requirements.