Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration

The RISC-V instruction set architecture (ISA) enjoys the flexibility for domain-specific custom instruction extensions. While the basic RISC-VISA contains common instructions, the extended accelerators provide additional computing power to meet diverse needs, making it well-suited for various emerging fields. High-level synthesis (HLS) provides a way to build hardware accelerators directly using RTL. It allows software engineers to create complex digital circuit designs using high-level languages such as C/C++, further improving development efficiency. However, verifying a design that includes RISC-V cores and custom extensions can be challenging. Traditional approaches for verifying HLS-generated designs use C-RTL co-simulation, which primarily focuses on the unit level, while making impractical assumptions about interactions between HLS-generated IPs and the processor. On the other hand, designs that combine RISC-V cores with custom extensions require system-level verification, which must extensively exercise both components and their interconnections. Furthermore, traditional C-RTL co-simulation performs cycle-accurate software simulation, which can be extremely time-consuming. To efficiently verify a RISC-V processor design with custom instruction extensions, we propose a novel verification framework that combines the benefits of the high-level abstraction of C/C++ simulation and cycle-accurate modeling of C-RTL co-simulations. We map the RISC-V core and the HLS-generated custom instruction accelerators, along with their corresponding C/C++ software models, onto the same FPGA with hardened processors allowing them to run simultaneously. A global monitor and checker carefully check the results of both the hardware and software in real-time. If a mismatch is detected, we capture a snapshot of the entire hardware, and reconstruct the simulation in external software simulators for detailed debugging. Through a series of benchmark experiments, results show a significant performance improvement over conventional approaches from 1419× to 9011×.