A DC-20 GHz 5-bit CMOS Digital Step Attenuator for Phased-array Applications

An attenuator serves as a crucial component in a phased array system, used to compensate amplitude errors induced by phase shifters and to mitigate sidelobe levels in the array antenna elements, thereby improving the directivity of the system. This paper presents a DC-20 GHz 5-bit digital step attenuator (DSA) with 0.5dB resolution in a 55-nm CMOS technology. The DSA is designed based on delicately ordered and cascaded T/π-type attenuation blocks, which are comprised of series/shunt switches employing triple-well isolated NMOS transistors with high isolation. Specially, the simplified T-type structure is utilized for attenuation cells of 0.5dB and 1dB, while the T-type and bridged T-type structures are employed for attenuation cells of 2dB and 4dB, respectively. The attenuation cell of 8dB adopts the switched π-type topology. Capacitive compensation technique is used for attenuation cells to minimize phase variations among all states. By carefully designing the order of the attenuation cells to improve impedance mismatches between them, the proposed DSA can achieve acceptable overall performance without the need for multiple bulky compensation inductors. The proposed DSA exhibits a 15.5-dB attenuation range with 0.5-dB tuning step. The simulated root mean square (RMS) amplitude and phase errors are less than 0.31dB and 1.18° over DC-20GHz, respectively. The simulated insertion loss is 2.6 to 5.7dB from DC to 20GHz. Moreover, the DSA chip occupies a small silicon area of 0.27mm
²
including all testing pads with a core size of only 0.011mm
²
.