Simulation Modeling of Output Clocking Signal Phase Deviation Depending on the Power of the Reference Sync Signal

The use of filters to reject the reference clock signal, when the clock signal is exposed to interference, leads to the need to use an intermittent clock signal in the frequency adjustment interval of the voltage-controlled oscillator (VCO), which in this case causes an increase in the phase deviation of the output clock signal due to a decrease in the power of the reference clock signal at the output of the narrow-band filter, used to isolate its carrier frequency. This article proposes a model for simulating the phase deviation of the clock signal, and also presents the numerical results of the simulation