An Efficient Aged Timing Analysis Method for Digital Integrated Circuit Under NBTI Effect

With the continuous development of semiconductor technology, the performance and integration of integrated circuits (ICs) have been continuously improved[1]. However, below the 65nm technology node, one of the aging effects of chips, the Negative Bias Temperature Instability (NBTI) effect, has become an important factor affecting the performance and reliability of digital integrated circuits[2]. This paper proposes an efficient aged timing analysis method for digital integrated circuit under NBTI effect. The method characterizes standard-cell aged library under a small number of typical input signal probability. Based on the established standard-cell aged library, timing model for perceiving NBTI aging is constructed through machine learning regression. The timing model established in this paper includes the mapping relationship between aged-related parameters and corresponding aged timing, with the input signal probability, input signal transition time, and output load capacitance of the cell as inputs, and the delay or output transition time of the cell as output. Based on the established timing model for perceiving NBTI effect, timing analysis of each cell in digital integrated circuits can be performed after degradation. Experimental results indicate that compared to existing methods, the approach presented in this paper reduces aged library usage by approximately 70% while only introducing small timing analysis error.