An Efficient Grouping Algorithm with Build-in-Self-Test for Multiple Memories

With the advancement of manufacturing processes and the ever-increasing demand for system-on-chip (SoC) computations, modern SoCs integrate a myriad of embedded memories, posing significant challenges for memory unit testing. Presently, the Memory Built-in-Self Test (MBIST) method is often used by the industry to effectively test memories. However, the burgeoning quantity of memories entails substantial resource waste when allocating test logic for each memory unit. It is imperative that the auxiliary circuitry for testing purposes remain minimal while fulfilling the testing requisites. Rational grouping of memories to share Built-In Self-Test (BIST) logic to mitigate unnecessary overhead during testing emerges as a plausible research problem. In this paper, we propose an efficient three-step partitioning approach for shared memory BIST logic, focusing on grouping rules and various constraints. This methodology is applicable to diverse memory types and BIST components. With the objective of minimizing the number of memory groups while satisfying constraints, our approach aims to reduce BIST logic, thereby mitigating area overhead. Following the initial partitioning to generate compatible memory groups, a multi- threaded approach is employed for the subsequent partitioning of all memory groups. By representing memories that satisfy distance constraints as graphs and substituting the greedy algorithm with the Bron-Kerbosch algorithm, superior solutions are attained. Experimental results indicate an average improvement of 6% in solution quality compared to the greedy algorithm.