Fast Design Technology Co-Optimization Framework for Emerging Technology with Hierarchical Graph Embedding

In the rapidly evolving landscape of semiconductor technology, the advent of novel materials and sophisticated device architectures offers both opportunities and challenges for researchers. Efficient optimization of power, performance, and area (PPA) is essential in order to fully take advantages of emerging materials and new device structures. To address aforementioned issues, this paper presents a novel fast design technology co-optimization (DTCO) framework for emerging flexible technologies. Simulation results demonstrate the advancement of our fast DTCO framework with over 100X speedup in both TCAD simulation and cell library characterization comparing to commercial tools. For a comprehensive DTCO iteration, covering TCAD simulation, modeling, cell library characterization and PPA evaluations, our framework achieves a runtime speedup between 1.9X to 14.1X depending on the scale of the evaluated circuits. The fast DTCO framework incorporates a graph neural network (GNN)-based TCAD surrogate model, a unified compact model, and a GNN-based cell library characterization model. The developed DTCO framework not only supports emerging technologies but can be applied to optimize the traditional silicon designs in advanced technology node.