Automated Design of a Strong-ARM Dynamic Comparator

This paper presents an automated design method for a Strong-ARM dynamic comparator. The dynamic characteristics of the dynamic comparator are analyzed and fitted into static characteristics, which is suitable for automatic sizing design with gm/ID method. The sizes of the transistors could be calculated by modeling the relationship with the specifications of the comparator, e.g., clock rate, power and input offset voltage. Furthermore, the automation process is implemented through an analog design tool Tsinghua Electronic Design (TED) and the design flow of the Strong-ARM dynamic comparator was verified at 40nm, 65nm and 180nm technologies respectively. Compared with the performance specifications, the maximum error of the simulation results of the input offset voltage and power consumption is approximately 3% and 6% respectively. Among them, the power consumption obtained from simulation are all lower than the performance specifications.