CGAT- TICER: A Compressed GAT-based TICER for RC Reduction

Model order reduction (MOR) is an effective method to reduce the circuit simulation time. As a conventional MOR method, Time Constant Equilibration Reduction (TICER) is used widely in fast interconnect analysis. Recently GCN-TICER is proposed by converting the node elimination speed-up problem into the classification issue using GCN-based anomaly detection. However, poor accuracy of node classification leads to insufficient efficiency. Besides, numerous unnecessary computations result in the high cost of elimination due to the uncompacted model. In this paper, we propose an improved algorithm CGAT- TICER using an anomaly detection method based on Graph Attention Network (GAT) to improve the accuracy of node classification. At the same time, we discard irrelevant elements to obtain a compressed model, thus reducing the elimination time. We conduct experiments on 6 cases ranging from 2K to 1M nodes in size from a clock-tree network. Experiments show that our algorithm achieves a 1.34x to 17.23× speedup compared to TICER, which is twice the SOTA GCN-TICER. The max relative error is less than 1.106%, which is 0.124% to 0.952% larger than TICER but smaller than GCN-TICER.