System Routing and TDM Assignment Optimization in Multi-2.5D FPGA-Based Prototyping Systems

2.5-D FPGA has been used in many Multi-FPGA Systems (MFS) for prototype verification due to its higher logic capacity and larger number of pins. The FPGA is composed of multiple dies connected with special wires. Due to the limited connections, FPGA-based system-level routing may cause internal congestion and lead to implementation failures. In addition, Time-Division Multiplexing (TDM) is used in inter-FPGA connections to improve logic utilization, and each signal is assigned a TDM ratio. However, the increase in inter-FPGA delay of signals positively correlated with the ratio. And the system performance will be significantly influenced by these internal congestions and TDMs. In this paper, a system-level routing framework with hybrid initial routing and two-stage reroute algorithms that generates legal and high-quality routing results for a 2.5-D MFS is proposed. Afterwards, a three-step framework is proposed to generate legal TDM ratios and optimize the system's performance, where a high-quality discretization algorithm based on bottom-up dynamic programming is implemented to optimize the performance losses. The experimental results demonstrate an average improvement of 8% in the solution's quality compared with our baseline algorithms within reasonable runtime. And compared with the winner of the 5
^th
EDA Elite Challenge, the quality of our solutions achieved the best results in most cases.