Multi-Dimensional Acceleration of Fault Simulation on ARM Multicore CPU

With the rapid increase in the scale of Very Large Scale Integration (VLSI), the runtime of fault simulation becomes a crucial issue during the test development phase of the VLSI design process. Various acceleration techniques have been pro-posed across different dimensions. However, a single technique may struggle to comprehensively address the multiple challenges in the fault simulation domain. This paper optimizes existing multi-threaded fault simulation algorithms on ARM multi-core processors. Firstly, the baseline single-threaded fault simulation algorithm was implemented with various optimization techniques such as event-driven, fault collapsing, and ARM NEON. Secondly, based on the analysis of uneven workloads in a previous multi-threaded algorithm, we present a fault-block allocation strategy to balance workloads among threads, which adopts parallel pattern single fault propagation and FFR-based fault sorting as well, to effectively reduce simulation path disparities among dif-ferent threads. Experimental results conducted on the Kunpeng 920 processor demonstrate the effectiveness of the implemented algorithm with integrated multiple optimization techniques.