Single Event Upset and Radiation Hardening of the Complementary FET (CFET) based 6T-SRAM

The CFET architecture addresses sub-3 nm technology challenges by reducing transistor footprint while maintaining performance. Our study employs 3D TCAD simulations to analyze SEU in four CFET 6T -SRAM architectures, identifying sensitive areas and LET thresholds. We propose a staggered architectures to enhance radiation Hardening and simplify routing, alongside structural optimizations for enhanced SEU hardening. These advancements aim to bolster reliability and efficiency in next generation semiconductor technologies.