DUET: FPGA-Accelerated Differential Testing Framework for Efficient Processor Verification

With the increasing complexity of modern proces-sors, verification becomes the main bottleneck in the entire processor development cycle, which can occupy up to 70% of the development time. Primarily this is because multiple iterations of debugging and software simulations are extremely time-consuming. To improve the verification and debugging efficiency, re-cent studies investigated differential testing techniques such as DiffTest, which dynamically compares the runtime results from the hardware design-under-test (DUT) and its software reference model. However, the slow speed of software simulation constrains the efficiency and effectiveness of these verification techniques. Although FPGAs can speed up the simulation, current methods either offer limited visibility into design details or are costly when dynamically checking against a reference model at the system level. In this paper, we present DUET, an FPGA accelerated differen-tial testing technique that combines the fine-grained debugging capability of DiffTest and the high simulation speed of FPGA prototyping. We evaluate the proposed method with practical RISC- V processors and demonstrate that the proposed approach accelerates verification efficiency up to 20x while preserving full visibility and debugging capabilities.