Virtual Fab Coupled Physics-Based Simulation Design of Sub-2nm Node 3D Heterogeneous Si/IGZO 6T SRAM

In this work, we propose an all-vertical-transistor based 3D heterogeneous 6T SRAM design. Self-align Si vertical gate-all-around (vGAA) FEOL CFET inverters and vertical channel all around (vCAA) BEOL-compatible IGZO pass gates (PG) are stacked vertically again in 3 layers within a 2T footprint area. State-of-the-art Virtual Fab process emulation validates the hetero-integration flow and generate near realistic geometry of not only the transistor but also the interconnect of a 6T SRAM cell. Furthermore, by physics-based simulation augmented fine tuning and extending the experimental validated device compact model and the interconnect RC, geometry- and parasitic-aware device to circuit DTCO analysis of the 3D heterogeneous 6T SRAM is performed. The hetero-integration of IGZO vCAA PG and vGAA CFET inverters showed 59% Read Static Noise Margin (RSNM) enhancement, 86% static leakage power reduction, and 53% area reduction.