ERL-LS: Accelerating Primitive Sequence Generation of Logic Synthesis with Evolutionary Reinforcement Learning

In VLSI design, logic synthesis (LS) converts a high-level description of a circuit to a gate-level netlist, generally using a unified heuristic algorithm to optimize different combi-national circuits. LS relies on a series of optimization commands to conduct the optimization, but the complexity of synthesis optimization flow increases exponentially with more commands used. Methods based on machine learning are widely used in LS. In particular, reinforcement learning (RL) is a very efficient method for exploring the customized circuit design space. For rapid LS, we propose an evolutionarily scheduled reinforcement Learning (ERL) framework, which is compatible with various agents adopted in prior RL-based LS works. Owing to the parallel execution on a multi-core processor, it can significantly improve exploration efficiency without losing solution quality. Our experiments show that, on EPFL benchmark and executing with 4 cores, our framework with RL agent in DRiLLS generally achieves 3.37 times speed-up to reach global optimal compared to the corresponding work. Our code is available at: github.com/Intelligent-Computing- Research-GroupIERL- LS.