Towards Smart Industrial Hardware Formal Verification

Formal verification has emerged as an alternative approach to guaranteeing the quality and accuracy of hardware designs, surpassing the limitations of traditional validation techniques like simulation and testing. However, as the number of state variables in the system increases, the size of the system state space expands exponentially, leading to the inevitable occurrence of the state explosion problem. Unlike the academic community, which has primarily focused on verification techniques, our approach emphasizes more intelligent modeling and data-driven acceleration.