Subgraph Matching with Diversity Handling and Its Applications to PCB Placement

Printed circuit board (PCB) placement is a critical stage in industrial chip design, which still heavily relies on manual methods, leading to substantial design time consumption. Given the frequent occurrence of similar or identical modules in different PCB designs, the reuse of placements emerges as a promising avenue to enhance the efficiency of PCB placement. In this paper, we propose a sub graph matching based reference placement algorithm to achieve PCB placement reuse, thereby improving placement efficiency. We first take the netlist of the already placed and unplaced circuits as input and abstract them into graphs. Then, we construct and filter candidate spaces based on the characteristics of components and nets. In the process of filtering candidate spaces, we adopt diversity handling that includes cut edges and block nodes to ensure the proposed algorithm can handle inexact matching. Finally, we introduce virtual nodes to construct a matching tree using a combination of depth-first search (DFS) and breadth-first search (BFS), and then perform hierarchical matching based on this matching tree to complete the sub graph matching and obtain the placement results. Experimental results show that in large-scale PCB cases, our algorithm runs much faster than the state-of-the-art works. Particularly, the matching rate of our algorithm is almost 100% for the tested cases.