CAPEDL: Cycle-Accurate Power Estimation with Deep Learning

A cycle-accurate power estimation model plays a crucial role in the early stages of chip design, which can assist the chips to meet the power, performance, and area (PPA) requirements. PPA are critical factors in determining the overall quality and success of a chip design, as they directly impact its efficiency, speed, and cost-effectiveness. While commercial electronic design automation (EDA) tools such as PrimeTimePX are currently employed for power analysis, their efficiency remains notably low. In this paper, we propose a novel framework, named CAPEDL, which can address the limitations of traditional approaches and improve the accuracy of power consumption estimation. CAPEDL utilizes a two-step deep learning network comprising an auto-encoder network for signal compression and a multilayer perceptron (MLP) model for power estimation. We use various circuits to evaluate the effectiveness of the CAPEDL framework. The experimental results show that CAPEDL outperforms the state-of-the-art approaches, with a normalized root mean squared error (NRMSE) of less than 3% and an average power error of less than 1%.