Study on Hardware Trojan Design and Implantation Based on Chisel

As the complexity and scale of digital integrated circuits increase, the level of chip design and verification continues to improve, and traditional design languages can no longer meet current demands. In response to these challenges, the Chisel language has emerged, providing a new tool for hardware Trojan design. This paper presents the design of an AES-T100 hardware Trojan using the Chisel language. This hardware Trojan features an always-on design and steals key information through internal activation. Functional simulations and scheme verifications have been conducted, and the test results show that compared to a Verilog-designed hardware Trojan, the Chisel-designed hardware Trojan chip achieves a maximum main frequency increase of 74.41MHz and a throughput increase of 25%, while only occupying 0.21% of the total code’s logic utilization. This demonstrates Chisel’s significant advantages and resource efficiency in hardware Trojan circuit design. Therefore, Chisel possesses higher efficiency and optimization capabilities in hardware design, making it highly valuable for research in hardware Trojans.