A Hardware Efficient Implementation of Sub-Block Interleaver for Polar Codes in 5G NR

In the fast-paced realm of Fifth-Generation (5G) and next-generation wireless technologies, the pursuit of efficiency and speed reaches new heights. Amidst the complexity of implementing error correcting codes, lies a daunting challenge to achieve reduced resource utilization and low latency without compromising performance. Hence the emphasis of this work is to reduce the latency and resource utilization of sub-block interleaving process used in the rate-matching of polar codes in 5G NR. The implementation of the modulus division function and the floor function in sub-block interleaving of polar codes to obtain the interleaved address is quite a difficult task. To address this challenge, this paper presents a novel Counter Based Sub-block interleaver (CBS) architecture for polar codes, suitable for 5G and beyond applications. A computationally less intensive and high-speed sub-block interleaver is proposed based on a simple algorithm, eliminating a few intricate arithmetic components, and generating the sub-block interleaved address. The proposed architecture is simulated for downlink and uplink channel specifications in MATLAB and Vivado design suite to verify the functionality of the design. For fair comparison, the proposed CBS for uplink and downlink channels is synthesized in Virtex-7 FPGA. The implementation results reveal that the proposed CBS achieves an 83% reduction in average resource utilization for the PDCCH channel compared to the existing implementations. The proposed CBS is 7.51 times faster than the conventional architecture. The CBS architecture is tested on Artix-7 (Basys-3) Board.