Designing a Compact Spiking Neural Network for Learning and Recognizing Digits on 180nm CMOS Process

Spiking Neural Network (SNN) is one of the most promising candidates for processing immense amounts of data at high speed and low power because parallel operation is one of its key advantages. In this research, we present a complete circuit-level design, implementation, and simulation of SNN for digits classification utilizing 180nm CMOS technology, together with on-chip training and inference. The proposed SNN includes Leaky Integrate-and-Fire (LIF) neurons and differentialamplifier-based synapses with Spike-Timing Dependent Plasticity (STDP) and Winner-Take-All mechanisms. Consequently, the proposed SNN is a compact CMOS circuit with 88 neurons and 312 synapses that is applied to the recognition of digit patterns. The average recognizing time for each digit is around $110 \mu \mathrm{s}$. Hence, the proposed SNN can recognize about 9090 patterns in one second.