Design of a low power high speed flash ADC

This paper’s primary goal is to offer potential solutions for creating low-power, high-speed flash ADC circuits. Traditionally, these circuits have required a 2 to the power of $\mathrm{N}: \mathrm{N}$ decoder circuitry to function, which in turn requires more power to manage because as bit count increases, so does circuit complexity. Here, the task is completed by modifying the conventional decoder circuit using two different methods: one uses a walltree-based circuit, and the other uses a mux-based decoder circuitry. These methods are implemented on the cadence virtuoso tool with 90nm technology.