A Wideband Divide-by-2/4 Static CML Frequency Divider With Quadrature Outputs

A wideband divide-by-2/4 frequency divider with quadrature outputs used in phase-locked loop (PLL) is designed in 22 -nm CMOS process in this paper. The divider consists of two cascade current-mode logic (CML) dividers as high-speed pre-scaler of the PLL, a multiplexer (MUX) is employed to select the divide-by- $2 / 4$ outputs. The frequency divider core circuit dissipates 3.6 mW at 1 V supply and the division range is from 0.07 to 31 GHz when the input power is 0 dBm. The phase noise can achieve to be ${- 1 4 8. 5} \mathrm{dBc} / \mathrm{H z}$ or $-152 \mathrm{dBc} / \mathrm{Hz}$ at 1 MHz offset and the phase mismatch between the in-phase $(I)$ and quadrature-phase $(Q)$ is ${1. 3}$ degree or 0.8 degree for the input frequency of 12 GHz when the division ratio is 2 or 4.