A Deterministic Concurrent-Routing Algorithm to Improve Wire Selection in FPGA Routing

An FPGA routing architecture consists of wire segments of different lengths. FPGA routers attempt to use longer wires for distant connections and shorter ones for closer connections. Due to the overhead associated with using longer wires, FPGA routers use them only when they have delay benefits over the shorter wires. The versatile place and route (VPR) is a popular open-source FPGA placement and routing tool. This work proposes a concurrent routing-based post-routing method for VPR to improve its utilization of longer wires. The proposed method builds an archive of routing trees using the VPR’s connection router and then solves an integer linear programming (ILP) problem to select routing trees for each net in such a way that the overall wire length is reduced with no effect on the critical path delay of the circuit. Experiments using Titan 23 benchmarks showed that it could reduce the utilization of larger wires by $4.43 \%$ on average without increasing the total wire length or critical path delay.