An Efficient Design Flow for Iterative Asynchronous Bundled-Data Circuits on FPGA

Asynchronous bundled-data circuits are promising alternatives to synchronous ones for designing low-power circuits because of their event-driven feature. However, the adoption of asynchronous circuits is hindered by limitations in commercial EDA tools, particularly concerning their ability to perform timing analysis and implement effective optimization techniques. This paper presents a design flow for implementing iterative ring-based asynchronous bundled-data circuits on FPGA with standard EDA tools. The design flow covers all essential steps, including hardware description, synthesis and implementation, and timing verification. To verify timing constraints, a novel technique called integrated timing propagation is introduced for performing timing analysis on multiple passive stages. The proposed design flow is employed to implement an advanced encryption standard circuit on the Xilinx Zynq-7000 FPGA, incorporating a phase-decoupled click template as handshaking controllers to facilitate the implementation of iterative rings. The results demonstrate that AES asynchronous BD circuits can achieve significant power savings and higher throughput-to-power ratios compared to AES synchronous circuits.