On-Chip Sensor to Monitor Aging Evolution in FinFET-Based Memories

Aging of electronics can be caused by various physical mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB) and electromigration (EM). Aging phenomena may lead to a degradation of performance and reliability of an electronic system, hence limiting its expected lifetime. The goal of this paper is twofold. First, it presents an advanced, miniature design of an aging sensor; second, it shows how this sensor is integrated with a commercial 5 nm FinFET-based SRAM IP core. The sensor is implemented with a small number of logic gates, resulting in negligible overhead in area, power and delay. The sensor is also equipped with power gating capability. Thus, during idle time, the sensor is temporarily disconnected from the power supply lines to prevent aging of its transistors. Experimental results based on extensive SPICE simulations demonstrate that this approach is able to detect even the slight increase in memory response time due to aging much earlier than a functional error is observed at the memory output. This solution enables mission-mode monitoring of memory operation, which is a critical aspect of silicon lifecycle management (SLM) framework.