Investigating the Feasibility of eFPGA-based Hardware Patching

System-on-Chip (SoC) designs are becoming increasingly complex, with the ability to detect and address all possible bugs at design time is highly challenging. Thus, to improve the survivability of SoC designs, it is desirable to be able to patch newly discovered design bugs or potential vulnerabilities in the field. Recently, the idea of hardware based patching, especially of hardware bugs, has emerged as a complementary approach to software/firmware-based post deployment updates. In anticipating potential problems, designers must invest an upfront cost to implement hardware-based patching infrastructures. In this paper, We investigate the feasibility of incorporating an embedded field-programmable gate array (eFPGA) fabric as an approach to enable hardware-based patching, i.e., reprogrammable hardware to patch hardware bugs. We propose, discuss, and evaluate three integration design architectures, characterizing the potential area and performance costs for each patching architecture and providing insights into how such architectures might be used to patch hardware bugs. Through a case study on an OpenPiton-based SoC, our results show the architectures’ area overhead costs ranging from $4.78 \%$ to $56.17 \%$, with latency arising from our example patches ranging from 1 to 2 cycles.